In the complex technology of today, many electronics designs require the use of large scale integrated (LSI) circuits. If these LSI circuits are custom designed and implemented, the design process requires a long period of gestation, typically 18 or more months; the circuit consequently becomes very expensive. In the prior art, an effort has been made to reduce the design time and expense of LSI circuits and yet meet the custom requirements of the users. This effort is in the form of a universal logic array where the user, by implementing certain interconnections on a predesigned LSI circuit, achieves a specialized LSI circuit which is essentially custom designed. This is the so-called "Programmable Logic Array (PLA)."
A typical prior art PLA is depicted in FIG. 1A. There, certain logic elements are grouped together in selected areas of the circuit array. This grouping has been determined to best meet the needs of most users. As an example, as shown in FIG. 1A, all the AND gates are grouped together on one side of the array, all the OR gates are grouped together on the opposite side, active elements are grouped in between and adjacent to the AND and OR groups, and input and output terminals are separately grouped on opposite sides of the array.
Although the PLA's of the prior art offer direct correspondence with the Boolean representation of a design, their usefulness as a logic design tool has been limited by small size and slow speed. The size is necessarily small because of the limited number of input and output ports that can be connected to the elements. This limits the number of logic functions that can be implemented. The speed is necessarily limited because of the separate grouping of elements, thereby necessitating less than optimal routing of signals and interconnection of logic elements. Some typical PLA's found in the prior art are as follows.
Texas Instrument (TI) has two types of PLA's, the TMS2000 and the 54S330. The former array has input and output ports numbering 17 and 18, respectively. The 54S330, on the other hand, has 12 input ports and 6 output ports only. The TMS2000 has an array size of 4,560 array cells, whereas the 54S330 has only an array size of 1,500. The TMS2000 is slow; its speed is 1,000 nanoseconds. The 54S330, however, has a speed of 35 nanoseconds.
Intersil and Signetics have PLA's also, the 5200 and the 82S100/200, respectively. The performance and characteristics of these PLA's are very much like the TI54S330: 14 input ports, 8 output ports, 65 nanoseconds and an array size of 728 for the 5200, and 16 input ports, 8 output ports, 35 nanoseconds and an array size of 1,920 for the 82S100/200.
IBM has a PLA that is significantly larger than the preceding ones: an array size of 7,280. Its output and input ports number 16 and 18, respectively. And its speed is 230 nanoseconds.
In contrast to these prior art PLA's, the array in accordance with the preferred embodiment performs with greater speed, viz., 2-5 nanoseconds. Furthermore, the array size is 15,625 and the input and output ports number 100. Unlike the majority of the prior art PLA's, the array in accordance with the invention has feedback elements, up to 500 in the preferred embodiment. It also contains flip flop elements numbering 250. The TI and IBM arrays have flip flop elements numbering only 8 and 13, respectively. Because of the speed, the greater number of input and output ports and greater array size, the array in accordance and with the invention provides a more flexible programmable array to better and more simply match logic designs.